Lecture VLSI Digital signal processing systems: Chapter 13 - Keshab K. Parhi

Chapter 13 - Bit level arithmetic architectures. This chapter includes content: Parallel multipliers, parallel multiplication with sign extension, baugh-wooley multipliers, parallel multipliers with modified booth recoding, interleaved floor-plan and bit-plane-based digital filters, design of bit-serial multipliers using systolic mappings,...

Từ khóa: VLSI Digital signal processing systems, Digital signal, Digital signal processing, DSP systems, Bit level arithmetic architectures, Parallel multipliers